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low power 250 msps 10-bit dac 1.8 v cmos direct digital synthesizer ad9913 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features 50 mw at up to 250 msps internal clock speed 100 mhz analog output integrated 10-bit dac 0.058 hz or better frequency resolution 0.022 phase tuning resolution programmable modulus in frequency equation phase noise C135 dbc per hz @ 1 khz offset (dac output) (<115 dbc per hz when using on-board pll multiplier) excellent dynamic performance >80 db sfdr @ 100 mhz (100 khz offset) a out automatic linear frequency sweeping capability 8 frequency or phase offset profiles 1.8 v power supply software and hardware controlled power-down parallel and serial programming options 32-lead lfcsp package optional pll ref_clk multiplier internal oscillator (can be driven by a single crystal) phase modulation capability applications portable and handheld equipment agile lo frequency synthesis programmable clock generator fm chirp source for radar and scanning systems general description the ad9913 is a complete direct digital synthesizer (dds) designed to meet the stringent power consumption limits of portable, handheld, and battery-powered equipment. the ad9913 features a 10-bit digital-to-analog converter (dac) operating up to 250 msps. the ad9913 uses advanced dds technology, coupled with an internal high speed, high performance dac to form a complete, digitally-program- mable, high frequency synthesizer capable of generating a frequency agile analog output sinusoidal waveform at up to 100 mhz. the ad9913 provides fast frequency hopping and fine tuning resolution. the ad9913 also offers fine resolution phase offset control. control words are loaded into the ad9913 through the serial or parallel i/o port. the ad9913 also supports a user- defined linear sweep mode of operation for generating highly linearized swept waveforms of frequency. to support various methods of generating a system clock, the ad9913 includes an oscillator, allowing a simple crystal to be used as the frequency reference, as well as a high speed clock multiplier to convert the reference clock frequency up to the full system clock rate. for power saving considerations, many of the individual blocks of the ad9913 can be powered down when not in use. the ad9913 operates over the extended industrial temperature range of ?40c to +85c. functional block diagram ref_clk input circuitry timing and control logic dds 10-bit dac user interface ad9913 07002-001 figure 1.
ad9913 rev. 0 | page 2 of 32 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications..................................................................................... 3 electrical specifications............................................................... 3 absolute maximum ratings............................................................ 5 esd caution.................................................................................. 5 equivalent circuits....................................................................... 5 pin configuration and function descriptions............................. 6 typical performance characteristics ............................................. 8 applications circuits...................................................................... 11 theory of operation ...................................................................... 12 dds core..................................................................................... 12 auxiliary accumulator .............................................................. 13 10-bit dac .................................................................................. 13 i/o port........................................................................................ 13 profile selections ........................................................................ 13 modes of operation ....................................................................... 14 single tone mode....................................................................... 14 direct switch mode ................................................................... 14 programmable modulus mode ................................................ 14 linear sweep mode.................................................................... 14 clock input (ref_clk)................................................................ 18 power-down features................................................................ 21 i/o programming........................................................................... 22 serial programming ................................................................... 22 parallel i/o programming......................................................... 23 register map and bit descriptions .............................................. 25 register map ............................................................................... 25 register bit descriptions........................................................... 27 outline dimensions ....................................................................... 31 ordering guide .......................................................................... 31 revision history 10/07revision 0: initial version
ad9913 rev. 0 | page 3 of 32 specifications electrical specifications avdd (1.8 v), dvdd (1.8 v), and dvdd_i/o = 1.8 v 5%, t = 25c, r set = 4.64 k, dac full-scale current = 2 ma, external reference clock frequency = 250 mhz with ref_clk multiplier disabled, unless otherwise noted. table 1. parameter conditions/comments min typ max unit ref_clk input characteristics frequency range ref_clk multiplier disabled 250 mhz enabled 250 mhz ref_clk input divider frequency full temperature range 83 mhz vco oscillation frequency vco1 16 250 mhz vco2 100 250 mhz pll lock time 25 mhz reference clock, 10 pll 60 s external crystal mode 25 mhz cmos mode vih 0.9 v vil 0.65 v input capacitance 3 pf input impedance (differential) 2.7 k input impedance (single-ended) 1.35 k duty cycle 45 55 % ref_clk input level 355 1000 mv p-p dac output characteristics full-scale output current 4.6 ma gain error ?14 ?6 %fs output offset +0.1 a differential nonlinearity ?0.4 +0.4 lsb integral nonlinearity ?0.5 +0.5 lsb ac voltage compliance range 400 mv spurious-free dynamic range refer to figure 6 serial port timing characteristics sclk frequency 32 mhz sclk pulse width low 17.5 ns high 3.5 ns sclk rise/fall time 2 ns data setup time to sclk 5.5 ns data hold time to sclk 0 ns data valid time in read mode 22 ns parallel port timing characteristics pclk frequency 33 mhz pclk pulse width low 10 ns high 20 ns pclk rise/fall time 2 ns address/data setup time to pclk 3.0 ns address/data hold time to pclk 0.3 ns data valid time in read mode 8 ns io_update/profile(2:0) timing setup time to sync_clk 0.5 ns hold time to sync_clk 1 sync_clk cycles
ad9913 rev. 0 | page 4 of 32 parameter conditions/comments min typ max unit miscellaneous timing characteristics wake-up time 1 fast recovery mode 1 sysclk cycles 2 full sleep mode 60 s reset pulse width high 5 sysclk cycles data latency (pipeline delay) frequency, phase-to-dac output matched latency enabled 11 sysclk cycles frequency-to-dac output matched latency disabled 11 sysclk cycles phase-to-dac output matched latency disabled 10 sysclk cycles delta tuning word-to-dac output (linear sweep) 14 sysclk cycles cmos logic inputs logic 1 voltage 1.2 v logic 0 voltage 0.4 v logic 1 current ?700 +700 na logic 0 current ?700 +700 na input capacitance 3 pf cmos logic outputs 1 ma load logic 1 voltage 1.5 v logic 0 voltage 0.125 v power supply current dvdd (1.8 v) pin current consumption 46.5 ma dac_clk_avdd (1.8 v) 4.7 ma dac_avdd (1.8 v) pin current consumption 6.2 ma pll_avdd (1.8 v) 1.8 ma clk_avdd (1.8 v) pin current consumption 4.3 ma power consumption single tone mode pll enabled, cmos input 50 66.5 mw pll disabled, differential input 57 70.5 mw pll enabled, xtal input 52 68.5 mw modulus mode pll disabled 94.6 mw linear sweep mode pll disabled 98.4 mw power-down full 15 mw safe pll enabled 44.8 mw pll modes vco 1 differential input mode 11 mw cmos input mode 7.5 mw crystal mode 5.4 mw vco 2 differential input mode 15 mw cmos input mode 11.5 mw crystal mode 9.4 mw 1 refer to the power-down features section. 2 sysclk cycle refers to the actual clock frequency used on-chip by the dds. if the reference clock multiplier is used to multip ly the external reference clock frequency, the sysclk frequency is the external frequency multiplied by the reference clock multiplication factor. if the reference clock multiplier and divider are not used, the sysclk frequency is the same as the external reference clock frequency.
ad9913 rev. 0 | page 5 of 32 absolute maximum ratings table 2. parameter rating maximum junction temperature 150c avdd, dvdd 2 v digital output current 5 ma storage temperature C65c to +150c operating temperature C40c to +105c lead temperature (soldering, 10 sec) 300c ja 36.1c/w jc 4.2c/w stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution equivalent circuits digital inputs input dvdd_i/o iout iout dac outputs avdd a void overdriving digital inputs. forward biasing esd diodes may c ouple digital noise onto power pins. must terminate outputs to agnd for current flow. do not exceed the output voltage compliance rating. 07002-002 figure 2. equivalent input and output circuits
ad9913 rev. 0 | page 6 of 32 pin configuration and fu nction descriptions pin 1 indicator 1 ps2/adr5/d5 2 ps1/adr4/d4 3 ps0/adr3/d3 4 dvdd 5 dgnd 6 adr2/d2 7 adr1/d1 8 adr0/d0 24 rset 23 agnd 22 avdd 21 agnd 20 iout 19 iout 18 agnd 17 avdd 9 s y n c _ c l k 1 0 s e r / p a r 1 1 a g n d 1 2 a v d d 1 3 r e f _ c l k 1 4 r e f _ c l k 1 5 a g n d 1 6 a v d d 3 2 a d r 6 / d 6 3 1 a d r 7 / d 7 3 0 s c l k ( p c l k ) 2 9 s d i o ( w r / r d ) 2 8 c s 2 7 i o _ u p d a t e 2 6 p w r _ d w n _ c t l 2 5 m a s t e r _ r e s e t top view (not to scale) ad9913 07002-003 figure 3. pin configuration table 3. pin function descriptions pin no. mnemonic i/o description 1 ps2/adr5/d5 i/o multipurpose pin: profile select pin (ps2) in direct switch mode, parallel port address line (adr5), and data line (d5) to program registers. 2 ps1/adr4/d4 i/o multipurpose pin: profile select pin (ps1) in direct switch mode or linear sweeping mode, parallel port address line (adr4), and data line (d4) to program registers. 3 ps0/adr3/d3 i/o multipurpose pin: profile select pin (ps0) in direct switch mode or linear sweeping mode, parallel port address line (adr3), and data line (d3) to program registers. 4 dvdd i digital power supply (1.8 v). 5 dgnd i digital ground. 6 adr2/d2 i/o parallel port address line 2 and data line 2. 7 adr1/d1 i/o parallel port address line 1and data line 1. 8 adr0/d0 i/o parallel port address line 0 and data line 0. 9 sync_clk o clock out. the profile pins [ps0:ps2] and the io_upd ate pin (pin 27) should be set up to the rising edge of this signal to maintain consta nt pipe line delay through the device. 10 ser /par i serial port and parallel port selection. logic low = serial mode; logic high = parallel mode. 11, 15, 18, 21, 23 agnd i analog ground. 12, 16, 17, 22 avdd i analog power supply (1.8 v). 13 ref_clk i reference clock input. see the ref_clk overview section for more details. 14 ref_clk i complementary referenc e clock input. see the ref_clk overview section for more details. 19 iout o open source dac complementary output source . current mode. connect through 50 to agnd. 20 iout o open source dac output source. current mode. connect through 50 to agnd. 24 rset i analog reference. this pin programs the dac outp ut full-scale reference current. attach a 4.64 k resistor to agnd. 25 master_reset i master reset, digital input (active high). this pin clears all memory elements and reprograms registers to default values.
ad9913 rev. 0 | page 7 of 32 pin no. mnemonic i/o description 26 pwr_dwn_ctl i external power-down, digital input (active high). a high level on this pin initiates the currently programmed power-down mode. see the power-down features section for further details. if unused, tie to ground. 27 io_update i i/o update; digital input. a high on this pin indicates a transfer of the contents of the i/o buffers to the corresponding internal registers. 28 cs i chip select for serial and parallel port. digital input (active low). bringing this pin low enables the ad9913 to detect serial (sclk) or parallel (pclk) clock rising/falling edges. bringing this pin high causes the ad9913 to ignore input on the data pins. 29 sdio( wr /rd) i/o bidirectional data line for serial port operatio n and write/read enable for parallel port operation. 30 sclk/pclk i input clock for serial and parallel port. 31 adr7/d7 i/o parallel port address line 7 and data line 7. 32 adr6/d6 i/o parallel port address line 6 and data line 6.
ad9913 rev. 0 | page 8 of 32 typical performance characteristics 0 0 20406080100120 frequency (mhz) power (dbm) ? 10 ? 20 ? 30 ? 40 ? 50 ? 60 ? 70 ? 80 ? 90 ? 100 07002-004 figure 4. wideband sfdr @ 99.76 mhz f out (250 mhz clock, 4 ma dac full-scale current, pll bypassed) 0 0 20406080100120 frequency (mhz) power (dbc) ? 10 ? 20 ? 30 ? 40 ? 50 ? 60 ? 70 ? 80 ? 90 ? 100 07002-005 figure 5. wideband sfdr @ 25.14 mhz f out (250 mhz clock, 4 ma dac full-scale current, pll bypassed) ? 50 ?90 00 . 07002-031 f out (% of system clock) sfdr (dbc) 4 5 ?55 ?60 ?65 ?70 ?75 ?80 ?85 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 1.7v 1.8v 1.9v figure 6. sfdr vs. supply variation (250 mhz clock, 4 ma dac full-scale current, pll bypassed) 0 ? 120 99.758381 99.783381 frequency (mhz) sfdr (dbm) ? 20 ? 40 ? 60 ? 80 ? 100 99.763381 99.768381 99.773381 99.778381 07002-007 figure 7. narrow-band sfdr @ 99.76 mhz f out (250 mhz clock, 4 ma dac full-scale current, pll bypassed) 0 ? 120 frequency (mhz) sfdr (dbm) ? 20 ? 40 ? 60 ? 80 ? 100 25.124918 25.174918 25.134918 25.144918 25.154918 25.164918 25.129918 25.139918 25.149918 25.159918 25.169918 07002-008 figure 8. narrow-band sfdr @ 25.14 mhz f out (250 mhz clock, 4 ma dac full-scale current, pll bypassed) ? 50 ?90 00 . 4 5 07002-032 f out (% of system clock) sfdr (dbc) ?55 ?60 ?65 ?70 ?75 ?80 ?85 +85oc ?40c +25c 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 figure 9. sfdr vs. temperature (250 mhz clock, 4 ma dac full-scale current, pll bypassed)
ad9913 rev. 0 | page 9 of 32 ? 50 ?90 0 250 07002-033 system clock (mhz) sfdr (dbc) ?55 ?60 ?65 ?70 ?75 ?80 ?85 50 100 150 200 39.88% 26.58% 10.21% figure 10. sfdr vs. system clock frequency (pll bypassed) ? 100 ?170 10 100m 07002-042 frequency (mhz) phase noise (dbc/hz) ?110 ?120 ?130 ?140 ?150 ?160 100 1k 10k 100k 1m 10m 92.3mhz 48.9mhz 23.1mhz 6.1mhz figure 11. residual phase noise vs. f out (pll bypassed) ? 150 ? 50 100 100m frequency (mhz) phase noise (dbc/hz) 1k 10k 100k 1m 10m ? 60 ? 70 ? 80 ? 90 ? 100 ? 110 ? 120 ? 130 ? 140 99mhz 12.5mhz 49mhz 25mhz 07002-012 figure 12. absolute phase noise vs. f out using the internal pll (ref_clk 25 mhz 10 = 250 mhz using pll) ? 50 ?90 00 07002-034 f out (% of system clock) sfdr (dbc) . 4 5 ?55 ?60 ?65 ?70 ?75 ?80 ?85 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 refspur pll 10 bypass figure 13. sfdr without the internal pll (ref_clk = 25 mhz 10 = 250 mhz using pll, 4 ma dac full-scale current)
ad9913 rev. 0 | page 10 of 32 ? 160 100 100m frequency (mhz) phase noise (dbc/hz) ? 60 ? 80 ? 140 1k 10k 100k 1m 10m ? 100 vco 1 vco 2 ? 120 07002-011 figure 14. absolute phas e noise, vco1 vs. vco2 40 0 50 250 07002-035 system clock frequency (mhz) power dissipation (mw) 35 30 25 20 15 10 5 70 90 110 130 150 170 190 210 230 dvdd avdd (pll) avdd (clk) avdd (dac) avdd (dac clk) figure 15. power supply current domains (cmos input mode, 4 ma dac full-scale current, single tone) 80 0 50 250 07002-036 system clock frequency (mhz) total power dissipated (mw) 70 60 50 40 30 20 10 70 90 110 130 150 170 190 210 230 diff input linear sweep cmos input linear sweep diff input single tone cmos input single tone figure 16. power dissipation vs. system clock frequency vs. clock input mode
ad9913 rev. 0 | page 11 of 32 applications circuits splitter lo + ? + ? + ? + ? ad9913 adc sideband selection filter 07002-013 figure 17. rfid block diagram (only i-channel of receiver shown) + ? crt display vga video filter signal band-pass filter input low-pass filter input attenuator local oscillator ad9913 as sweep generator 07002-014 figure 18. handheld spectrum analyzer
ad9913 rev. 0 | page 12 of 32 theory of operation dds core the dds block generates a reference signal (sine or cosine based on the selected dds sine output bit). the parameters of the reference signal (frequency and phase), are applied to the dds at its frequency and phase offset control inputs, as shown in figure 19 . 07002-030 system clock 32 15 frequency control angle to amplitude conversion (sine or cosine) phase offset control to dac msbs dq r accumulator reset 32 msb aligned dds signal control parameters 10 15 32 32 14 32-bit accumulator figure 19. dds block diagram the output frequency (f out ) of the ad9913 is controlled by the frequency tuning word (ftw) at the frequency control input to the dds. in all modes except for programmable modulus, the relationship between f out , ftw, and f sysclk is: sysclk out f ftw f ? ? ? ? ? ? = 32 2 (1) where ftw is a 32-bit integer ranging in value from 0 to 2,147,483,647 (2 31 ? 1), which represents the lower half of the full 32-bit range. this range constitutes frequencies from dc to nyquist (that is, ? f sysclk ). the ftw required to generate a desired value of f out is found by solving equation 1 for ftw as given in equation 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = sysclk out f f ftw 32 2round (2) where the round (x) function rounds the argument (the value of x) to the nearest integer. this is required because the ftw is constrained to be an integer value. for applications where rounding to the nearest available fre- quency is not acceptable, programmable modulus mode enables additional options. the relative phase of the dds signal can be digitally controlled by means of a 14-bit phase offset word (pow). the phase offset is applied prior to the angle-to-amplitude conversion block internal to the dds core. the relative phase offset (?) is given by ? ? ? ? ? ? ? ? ? ? ? ? =? 14 14 2 360 2 2 pow pow where the upper quantity is for the phase offset expressed as radian units and the lower quantity as degrees. to find the pow value necessary to develop an arbitrary ?, solve the above equation for pow and round the result (in a manner similar to that described for finding an arbitrary ftw in equation 1 and equation 2). ftw pow 1 0 external internal register map and timing control + dac iout iout rset dds core i/o port clock port ref_clk ref_clk pll multiplier clock selection ser/par cs sclk/pclk ad[7:0]/ps[2:0] master reset pwr_dwn_ctl io_update sync_clk 1 0 1 0 profile selections 1 0 1 0 z ?1 auxiliary accumulator angle to amplitude phase accumulator phase offset 07002-015 s d i o ( w r / r d ) 32 32 32 32 32 14 14 10 2 figure 20. detailed block diagram
ad9913 rev. 0 | page 13 of 32 auxiliary accumulator in addition to the phase accumulator of the dds, the ad9913 has an auxiliary accumulator. this accumulator can be con- figured to support either an automatic sweep of one of the programmable characteristics of the dds output (frequency or phase), or it can be configured to implement a change in the denominator of the frequency equation given in the dds core section. for further details, refer to the programmable modulus mode section. 10-bit dac the ad9913 incorporates an integrated 10-bit, current output dac. the output current is delivered as a balanced signal using two outputs. the use of balanced outputs reduces the potential amount of common-mode noise present at the dac output, offering the advantage of an increased signal-to-noise ratio. an external resistor (r set ) connected between the rset pin and agnd establishes the reference current. the full-scale output current of the dac (i out ) is produced as a scaled version of the reference current. the recommended value of r set is 4.62 k. the following equation computes the typical full-scale current with respect to the r set resistor value and the gain control setting: () x r rxi set set out += 1 0206.0 ),( the dac is designed to operate with full-scale current values up to 4.58 ma. based on the equation and assuming a 4.62 k resistor value for r set , and x = 0x1ff, the nominal output current for the dac is 2.28 ma. figure 17 shows the range of dac output current vs. the dac fs value assuming an r set value of 4.62 k. 5 0 0 1200 dac code dac full-scale current (ma) 4 3 2 1 200 400 600 800 1000 07002-016 figure 21. dac output cu rrent vs. dac fs bits pay careful attention to the load termination to ensure that the output voltage remains within the specified compliance range; voltages developed beyond this range cause excessive distortion and can damage the dac output circuitry. i/o port the ad9913 i/o port can be configured as a synchronous serial communications port that allows easy interface to many industry- standard microcontrollers and microprocessors. the serial i/o port is compatible with most synchron ous transfer formats, including both the motorola 6905/11 spi and intel 8051 ssr protocols. for faster programming requirements, a parallel mode is also provided. profile selections the ad9913 supports the use of profiles, which consist of a group of eight registers containing pertinent operating parameters for a particular operating mode. profiles enable rapid switching between parameter sets. profile parameters are programmed via the i/o port. once programmed, a specific profile is activated by means of register cfr1 bits [22:20], or three external profile select pins. the external profile pins option is only available in serial mode.
ad9913 rev. 0 | page 14 of 32 modes of operation the ad9913 operates in four modes: ? single tone ? direct switch ? programmable modulus ? linear sweep the modes relate to the data source used to supply the dds with its signal control parameters: frequency, phase, or ampli- tude. the partitioning of the data into different combinations of frequency, phase, and amplitude is handled automatically based on the mode and/or specific control bits. single tone mode single tone mode is the default operational mode and is active when both the direct switch mode bit and the auxiliary accumulator enable bit are not set. this mode outputs a single frequency as programmed by the user in the frequency tuning word (ftw) register. a phase offset value is also available in single tone mode via the pow register. direct switch mode direct switch mode enables fsk or psk modulation. this mode simply selects the frequency or phase value programmed into the profile registers. frequency or phase is determined by the destination bits in cfr1 [13:12]. direct switch mode is enabled using the direct switch mode active bit in register cfr1 [16]. two approaches are designed for switching between profile registers. the first is programming the internal profile control bits, cfr1 [22:20], to the desired value and issuing an io_update. the second approach, with higher data throughput, is achieved by changing the profile control pins [2:0]. control bit cfr1 [27] is for selection between the two approaches. the default state uses the profile pins. to perform 8-tone fsk or psk, program the ftw word or phase offset word in each profile. the internal profile control bits or the profile pins are used for the fsk or psk data. tabl e 4 shows the relationship between the profile selection pin or bit approach. table 4. profile selection profile pins ps [2:0] or cfr1 bits [22:20] profile selection 000 profile 0 001 profile 1 010 profile 2 011 profile 3 100 profile 4 101 profile 5 110 profile 6 111 profile 7 programmable modulus mode in programmable modulus mode, the auxiliary accumulator is used to alter the frequency equation of the dds core, making it possible to implement fractions which are not restricted to a power of 2 in the denominator. a standard dds is restricted to powers of 2 as a denominator because the phase accumulator is a set of bits as wide as the frequency tuning word. when in programmable modulus mode, the frequency equation becomes f 0 = ( ftw)(f s )/ x with 0 ftw 2 31 f 0 = f s (1 ? ( ftw / x )) with 2 31 < ftw < 2 32 ? 1 where 0 x 2 32 . when in programmable modulus mode, the auxiliary accumu- lator is set up to roll over before it reaches full capacity. every time it rolls over, an extra lsb value is added to the phase accumulator. in order to determine the values that must be programmed in the registers, the user must define the desired output to sampling clock frequency as a ratio of integers (m/n, where n must not exceed 2 32 ). n should be programmed into register 0x06 [63:32]. register 0x06 [31:0] must be programmed with the ftw which is the integer portion of ((2 32 f 0 )/ f s ). finally, register 0x07 [31:0] must be programmed with the modulus step which is the remainder of ((2 32 f 0 )/ f s ). linear sweep mode one purpose of linear sweep mode is to provide better bandwidth containment compared to direct switch mode by enabling more gradual, user-defined changes between a starting point (s0) to an endpoint (e0). the auxiliary accumulator enable bit is located in register cfr1 [11]. linear sweep uses the auxiliary accumulator to sweep frequency or phase from s0 to e0. a frequency or phase sweep is determined by the destination bits in cfr1 [13:12]. the trigger to initiate the sweep can be edge or level triggered. this is determined by register cfr1 [9]. note that, in level triggered mode, the sweep automatically repeats as long as the appropriate profile pin is held high. in linear sweep mode, s0 and e0 (upper and lower limits) are loaded into the linear sweep parameter register (register 0x06). if configured for frequency sweep, the resolution is 32-bits. for phase sweep, the resolution is 14 bits. when sweeping the phase, the word value must be msb-aligned; unused bits are ignored. the profile pins or the internal profile bits trigger and control the direction (up/down) of the linear sweep for frequency or phase. tabl e 5 depicts the direction of the sweep.
ad9913 rev. 0 | page 15 of 32 table 5. determining the direction of the linear sweep profile pins [2:0] or cfr1 bits [22:20] linear sweep mode x00 1 sweep off x01 1 ramp up x10 1 ramp down x11 1 bidirectional ramp 1 x = dont care. note that if the part is used in parallel port programming mode, the sweep mode is only determined by the internal profile control bits, cfr1 [22:20]. if the part is used in serial port programming mode, either the internal profile control bits or the external profile select pins can work as the sweep control. cfr1 [27] selects between these two approaches. setting the slope of the linear sweep the slope of the linear sweep is set by the intermediate step size (delta tuning word) between s0 and e0 (see figure 22 ) and the time spent (sweep ramp rate word) at each step. the resolution of the delta tuning word is 32 bits for frequency and 14 bits for phase. the resolution for the delta ramp rate word is 16 bits. in linear sweep mode, the user programs a rising delta word (rdw, register 0x07) and a rising sweep ramp rate (rsrr, register 0x08). these settings apply when sweeping from s0 to e0. the falling delta word (fdw, register 0x07) and falling sweep ramp rate (fsrr, register 0x08) apply when sweeping from e0 to s0. note that if the auxiliary accumulator is allowed to overflow, an uncontrolled, continuous sweep operation occurs. to avoid this, the magnitude of the rising or falling delta word should be smaller than the difference between full-scale and the e0 value (full-scale ? e0). for a frequency sweep, full-scale is 2 32 ? 1. for a phase sweep, full-scale is 2 14 ? 1. figure 22 displays a linear sweep up and then down. this depicts the dwell mode (see crf1 [8]). if the no-dwell bit, cfr1 [8], is set, the sweep accumulator returns to 0 upon reaching e0. s0 e0 time rdw fdw rsrr fsrr linear sweep (frequency/phase) f, p f, p t t 07002-037 figure 22. linear sweep mode for a piecemeal or a nonlinear transition between s0 and e0, the delta tuning words and ramp rate words can be reprogram- med during the transition. the formulas for calculating the step size of rdw or fdw are sysclk f rdw step frequency 32 2 (mhz) s 13 2 rdw stepphase (radians) 11 2 45 rdw stepphase (degrees) the formula for calculating delta time from rsrr or fsrr is (hz) / sysclk frsrrt at 250 msps operation, ( f sysclk =250 mhz). the minimum time interval between steps is 1/250 mhz 1 = 4 ns. the maximum time interval is (1/250 mhz) 65,535= 262 s. frequency linear sweep example in linear sweep mode, when sweeping from low to high, the rdw is applied to the input of the auxiliary accumulator and the rsrr register is loaded into the sweep rate timer. the rdw accumulates at the rate given by the ramp rate (rsrr) until the output equals the upper limit in the linear sweep parameter register (register 0x06). the sweep is then complete. when sweeping from high to low, the fdw is applied to the input of the auxiliary accumulator and the fsrr register is loaded into the sweep rate timer. the fdw accumulates at the rate given by the ramp rate (fsrr) until the output equals the lower limit in the linear sweep parameter register value (register 0x06). the sweep is then complete. a phase sweep works in the same manner with fewer bits. to view sweep capabilities using the profile pins and the no- dwell bit, refer to figure 23 , figure 24 , and figure 25 .
ad9913 rev. 0 | page 16 of 32 ramp-up mode (edge triggered) ramp-up mode (level triggered) e0 s0 ps[0] ps[1] e0 s0 ps[0] ps[1] no-dwell bit = 0 no-dwell bit = 1 e0 s0 ps[0] ps[1] e0 s0 ps[0] ps[1] no-dwell bit = 0 no-dwell bit = 1 07002-040 ramp-down mode (edge triggered) ramp-down mode (level triggered) e0 s0 ps[0] ps[1] e0 s0 ps[0] ps[1] e0 s0 ps[0] ps[1] e0 s0 ps[0] ps[1] no-dwell bit = 0 no-dwell bit = 1 no-dwell bit = 0 no-dwell bit = 1 07002-041 figure 23. display of ramp-up and ramp-down capability using the external profile pins
ad9913 rev. 0 | page 17 of 32 e0 s0 ps[0] ps[1] bidirectional mode (edge triggered) no-dwell bit = x bidirectional mode (level triggered) no-dwell bit = 0 no-dwell bit = 1 e0 s0 ps[0] ps[1] e0 s0 ps[0] ps[1] 07002-043 figure 24. display of bidirectional ramp capability using the external profile pins combination of modes (edge triggered) e0 s0 ps[0] ps[1] ramp up mode ramp up mode bidirectional mode ramp down mode 07002-044 figure 25. combination of sweep modes using the external profile pins clear functions the ad9913 allows for a programmable continuous zeroing of the sweep logic and the phase accumulator as well as clear-and- release, or automatic zeroing function. each feature is individually controlled via bits in the control registers. continuous clear bits the continuous clear bits are simply static control signals that hold the respective accumulator (and associated logic) at zero for the entire time the bit is active. clear-and-release function the auto clear auxiliary accumulator bit, when active, clears and releases the auxiliary accumulator upon receiving an i/o_update or change in profile bits. the auto clear phase accumulator, when active, clears and releases the phase accumulator upon receiving a i/o_update or a change in profile bits. the automatic clearing function is repeated for every subsequent i/o_update or change in profile bits until the control bit is cleared. these bits are programmed independently and do not have to be active at the same time. for example, one accumulator may be using the clear and release function while the other is continuously cleared.
ad9913 rev. 0 | page 18 of 32 clock input (ref_clk) ref_clk overview the ad9913 supports a number of options for producing the internal sysclk signal (that is , the dac sample clock) via the ref_clk input pins. the ref_clk input can be driven directly from a differential or single-ended source, or it can accept a crystal connected across the two input pins. there is also an internal phase-locked loop (pll) multiplier that can be independently enabled. the various input configurations are controlled by means of the control bits in the cfr2 [7:5] register. table 6. clock input mode configuration cfr2 [7:5] mode configuration 000 differential input, pll enabled 001 differential input, pll disabled (default) x10 1 xtal input, pll enabled x11 1 xtal input, pll disabled 100 cmos input, pll enabled 101 cmos input pll disabled 1 x = dont care. xtal ref_clk ref_clk cmos 1 0 1 0 10 00 1 0 1 0 2 2 pll cfr2[5] cfr2[6] divide control cfr2[5:0] cfr2[14:9] differential/ single cfr2[15] cfr2[3] cfr2[7:6] 13 14 system clock 07002-020 figure 26. internal clock path functional block diagram crystal-driven ref_clk when using a crystal at the ref_clk input, the resonant frequency should be approximately 25 mhz. figure 27 shows the recommended circuit configuration. refclk refclk 39pf 39pf xtal 13 14 07002-021 figure 27. crystal connection diagram direct-driven ref_clk when driving the ref_clk inputs directly from a signal source, either single-ended or differential signals can be used. with a differential signal source, the ref_clk pins are driven with complementary signals and ac-coupled with 0.1 f capacitors. with a single-ended signal source, either a single- ended-to-differential conversion can be employed or the ref_clk input can be driven single-ended directly. in either case, 0.1 f capacitors are used to ac couple both ref_clk pins to avoid disturbing the internal dc bias voltage of ~1.35 v. see figure 28 for more details. the ref_clk input resistance is ~2.7 k differential (~1.35 k single-ended). most signal sources have relatively low output impedances. the ref_clk input resistance is relatively high, therefore, its effect on the termination impedance is negligible and can usually be chosen to be the same as the output imped- ance of the signal source. the bottom two examples in figure 28 assume a signal source with a 50 output impedance. termination ref_clk differential source, differential input single-ended source, differential input s ingle-ended source, single-ended input 13 14 0.1f 0.1f lvpecl, or lvds driver ref_clk 13 14 50 ? 0.1f 0.1f balun (1:1) ref_clk ref_clk ref_clk ref_clk 13 14 0.1f 0.1f 50 ? 07002-022 figure 28. direct connection diagram cmos-driven ref_clk this mode is enabled by writing cfr2 [7] to be true. in this state, the ad9913 must be driven at pin 13 with the reference clock source. additionally, it is recommended that pin 14 in cmos mode be tied to ground through a 10 k resistor. 13 14 ref_clk ref_clk 10k ? cmos drive r 0 7002-023 figure 29. cmos-driven diagram phase-locked loop (pll) multiplier an internal phase-locked loop (pll) provides users of the ad9913 the option to use a reference clock frequency that is lower than the system clock frequency. the pll supports a wide range of programmable frequency multiplication factors (1 to 64). see table 7 for details on configuring the pll multipli- cation factor. the pll is also equipped with a pll_lock bit. cfr2 [15:8] and cfr2 [5:1] control the pll operation. upon power-up, the pll is off. to initialize the pll, cfr2 [5] must be cleared and cfr2 [1] must be set. the function of cfr2 [1]
ad9913 rev. 0 | page 19 of 32 is to reset digital logic in the pll circuit with an active low signal. the function of cfr2 [5] is to power up or power down the pll. cfr2 [4] is the pll lo range bit. when operating the ad9913 with the pll enabled, cfr2 [4] adjusts pll loop filter components to allow low frequency reference clock inputs. cfr2 [3] enables a divide-by-two circuit at the input of the pll phase detector. if this bit is enabled the reference clock signal is divided by 2 prior to multiplication in the pll. refer to the electrical specifications for the maximum reference clock input frequency when utilizing the pll with the divide by 2 circuit enabled. if the divide by 2 circuit is disabled and the pll is enabled, then the maximum reference clock input frequency is one-half the maximum rate indicated in the electrical specifications table for the maximum input divider frequency. the ad9913 pll uses one of two vcos for producing the system clock signal. cfr2 bit 2 is a select bit that enables an alternative vco in the pll. the basic operation of the pll is not affected by the state of this bit. the purpose of offering two vcos is to provide performance options. the two vcos have approximately the same gain characteristics, but differ in other aspects. the overall spurious performance, phase noise, and power consumption may change based on the setting of cfr2 bit 2. it is important to consider that for either vco, the minimum oscillation frequency must be satisfied, and that minimum oscillation frequency is significantly different between the two oscillators. cfr2 [15:9], along with cfr2 [3], determine the multiplication of the pll. cfr2 [15] enables a divider at the output of the pll. the bits cfr [14:9] control the feedback divider. the feedback divider is composed of two stages: n (1:31) selected by cfr2 [13:9]; 1 or 2 selected by cfr2 [14]. note that the same system clock frequency can be obtained with different combinations of cfr2 [15:9] and cfr2 [3]. one combination may work better in a given application either to run at lower power or to satisfy the vcos minimum oscillation frequency note that the ad9913 maximum system clock frequency is 250 mhz. if the user intends to use high values for the pll feedback divider ratio, then care should be taken that the system clock frequency does not exceed 250 mhz. pll lock indication cfr2 [0] is a read-only bit that displays the status of the pll lock signal. when the ad9913 is programmed to use the pll, there is some amount of time required for the loop to lock. while the loop is not locked, the chip system clock operates at the reference clock frequency presented to the part at the pins. once the pll lock signal goes high, the system clock frequency switches asynchronously to operate at the pll output frequency. to maintain a system clock frequency with or without a locked loop if the pll lock signal transistions low, the chip reverts to the reference clock signal while the loop attempts to acquire lock once again. table 7 describes how to configure the pll multiplication factor using the appropriated register bits.
ad9913 rev. 0 | page 20 of 32 table 7. pll multiplication factor configuration cfr2 [15:14], cfr2 [3] cfr2 [13:9] = 000 = 001 = 100 = 101 = 010 = 011 = 110 = 111 00000 32 16 16 8 64 32 32 16 00001 1 0.5 0.5 0.25 2 1 1 0.5 00010 2 1 1 0.5 4 2 2 1 00011 3 1.5 1.5 0.75 6 3 3 1.5 00100 4 2 2 1 8 4 4 2 00101 5 2.5 2.5 1.25 10 5 5 2.5 00110 6 3 3 1.5 12 6 6 3 00111 7 3.5 3.5 1.75 14 7 7 3.5 01000 8 4 4 2 16 8 8 4 01001 9 4.5 4.5 2.25 18 9 9 4.5 01010 10 5 5 2.5 20 10 10 5 01011 11 5.5 5.5 2.75 22 11 11 5.5 01100 12 6 6 3 24 12 12 6 01101 13 6.5 6.5 3.25 26 13 13 6.5 01110 14 7 7 3.5 28 14 14 7 01111 15 7.5 7.5 3.75 30 15 15 7.5 10000 16 8 8 4 32 16 16 8 10001 17 8.5 8.5 4.25 34 17 17 8.5 10010 18 9 9 4.5 36 18 18 9 10011 19 9.5 9.5 4.75 38 19 19 9.5 10100 20 10 10 5 40 20 20 10 10101 21 10.5 10.5 5.25 42 21 21 10.5 10110 22 11 11 5.5 44 22 22 11 10111 23 11.5 11.5 5.75 46 23 23 11.5 11000 24 12 12 6 48 24 24 12 11001 25 12.5 12.5 6.25 50 25 25 12.5 11010 26 13 13 6.5 52 26 26 13 11011 27 13.5 13.5 6.75 54 27 27 13.5 11100 28 14 14 7 56 28 28 14 11101 29 14.5 14.5 7.25 58 129 129 14.5 11110 30 15 15 7.5 60 30 30 15 11111 31 15.5 15.5 7.75 62 31 31 15.5
ad9913 rev. 0 | page 21 of 32 power-down features the ad9913 supports an externally controlled power-down feature as well as software programmable power-down bits consistent with other analog devices, inc. dds products. the external pwr_dwn_ctl pin determines the power- down scheme. a low on this pin allows the user to power down dac, pll, input clock circuitry, and the digital section of the chip individually via the unique control bits, cfr1 [6:4]. in this mode, cfr1 [7] is inactive. when the pwr_dwn_ctl is set, cfr1 [6:4] lose their meaning. at the same time, the ad9913 provides two different power-down modes based on the value of cfr1 [7]: a fast recovery power-down mode in which only the digital logic and the dac digital logic are powered down, and a full power-down mode in which all functions are powered down. a significant amount of time is required to recover from power-down mode. tabl e 11 indicates the logic level for each power-down bit that drives out of the ad9913 core logic to the analog section and the digital clock generation section of the chip for the external power-down operation. table 8. power-down controls control mode active description pwr_dwn_ctl = 0 cfr1 [7] = dont care software control digital power-down = cfr1 [6] dac power-down = cfr1 [5] input clock power-down = cfr1 [4] pwrdwnctl = 1 cfr1 [7] = 0 external control, fast recovery power-down mode n/a pwrdwnctl = 1 cfr1 [7] = 1 external control, full power- down mode n/a
ad9913 rev. 0 | page 22 of 32 i/o programming serial programming the ad9913 serial port is a flexible, synchronous serial communications port allowing an easy interface to many industry standard microcontrollers and microprocessors. the serial i/o is compatible with most synchronous transfer formats, including both the motorola 6905/11 spi and intel 8051 ssr protocols. the interface allows read/write access to all registers that configure the ad9913. msb first or lsb first transfer formats are supported. the ad9913 serial interface port is configured as a single pin i/o (sdio), which allows a two-wire interface. the ad9913 does not have a sdo pin for 3-wire operation. with the ad9913, the instruction byte specifies read/write operation and the register address. serial operations on the ad9913 occur only at the register level, not the byte level. for the ad9913, the serial port controller recognizes the instruction byte register address and automatically generates the proper register byte address. in addition, the controller expects that all bytes of that register are accessed. it is a requirement that all bytes of a register be accessed during serial i/o operations. there are two phases to a communication cycle with the ad9913. phase 1 is the instruction cycle, which is the writing of an instruction byte into the ad9913, coincident with the first eight sclk rising edges. the instruction byte provides the ad9913 serial port controller with information regarding the data transfer cycle, which is phase 2 of the communication cycle. the phase 1 instruction byte defines whether the upcoming data transfer is read or write and the serial address of the register being accessed. the first eight sclk rising edges of each communication cycle are used to write the instruction byte into the ad9913. the remaining sclk edges are for phase 2 of the communication cycle. phase 2 is the actual data transfer between the ad9913 and the system controller. the number of bytes transferred during phase 2 of the communication cycle is a function of the register accessed. for example, when accessing the control function register 2, which is two bytes wide, phase 2 requires that two bytes be transferred. if accessing one of the profile registers, which are six bytes wide, phase 2 requires that six bytes be transferred. after transferring all data bytes per the instruction, the communication cycle is completed. at the completion of any communication cycle, the ad9913 serial port controller expects the next eight rising sclk edges to be the instruction byte of the next communication cycle. all data input to the ad9913 is registered on the rising edge of sclk. all data is driven out of the ad9913 on the falling edge of sclk. figure 30 through figure 32 illustrate the general operation of serial ports. i 7 sdio instruction cycle data transfer cycle scl k cs i 6 i 5 i 4 i 3 i 2 i 1 i 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 07002-025 figure 30. serial port writing timingclock stall low i 7 sdio instruction cycle data transfer cycle s cl k cs i 6 i 5 i 4 i 3 i 2 i 1 i 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 07002-026 figure 31. serial port write timingclock stall high i 7 sdio instruction cycle data transfer cycle scl k cs i 6 i 5 i 4 i 3 i 2 i 1 i 0 d o7 d o6 d o5 d o4 d o3 d o2 d o1 d o0 07002-027 figure 32. two-wire serial port read timingclock stall high
ad9913 rev. 0 | page 23 of 32 instruction byte the instruction byte contains the following information as shown in the instruction byte bit map. instruction byte information bit map msb lsb d7 d6 d5 d4 d3 d2 d1 d0 r/ w x x a4 a3 a2 a1 a0 r/ w bit 7 of the instruction byte determines whether a read or write data transfer occurs after the instruction byte write. logic high indicates read operation. logic 0 indicates a write operation. x, xbit 6 and bit 5 of the instruction byte are dont care. a4, a3, a2, a1, a0bit 4, bit 3, bit 2, bit 1, and bit 0 of the instruction byte determine which register is accessed during the data transfer portion of the communications cycle. serial interface port pin description sclkserial port clock the serial clock pin is used to synchronize data to and from the ad9913 and to run the internal state machines. cs chip select active low input that allows more than one device on the same serial communications line. the sdio pin goes to a high impedance state when this input is high. if driven high during any communications cycle, that cycle is suspended until chip select is reactivated low. chip select can be tied low in systems that maintain control of sclk. sdioserial data i/o. data is always written into and read from the ad9913 on this pin. msb/lsb transfers the ad9913 serial port can support both most significant bit (msb) first or least significant bit (lsb) first data formats. this functionality is controlled by the cfr1 [23]. the default value is msb first. the instruction byte must be written in the format indicated by control register 0x00 bit 8. that is, if the ad9913 is in lsb first mode, the instruction byte must be written from least significant bit to most significant bit. for msb first operation, the serial port controller generates the most significant byte (of the specified register) address first followed by the next less significant byte addresses until the i/o operation is complete. all data written to (read from) the ad9913 must be in msb first order. if the lsb mode is active, the serial port controller generates the least significant byte address first followed by the next greater significant byte addresses until the i/o operation is complete. all data written to (read from) the ad9913 must be in lsb first order. notes on serial port operation the lsb first bit resides in cfr1 [23]. note that the configuration changes immediately upon writing to the byte containing the lsb first bit. therefore, care must be taken to compensate for this new configuration for the remainder of the current communication cycle. reading profile registers requires that the external profile select pins (ps[2:0]) be configured to select the corresponding register. parallel i/o programming parallel port interface pin description cs chip select an active low on this pin indicates that a read/write operation is about to be performed. if this pin goes high during an access, the parallel port is reset to its initial condition. r/ w read/write a high on pin 29 combined with cs active low indicates a read operation. a low on this pin indicates a write operation. pclkparallel port clock the parallel clock pin is used to synchronize data to and from the ad9913 and to run the internal state machines. addr/data [7:0] the 8-bit address/data bus. it wo rks in a bidirectional fashion to support both read and write operations. notes on parallel port operation each operation works in a 3-pclk cycle with the first clock cycle for addressing, the second for reading or writing, and the third for re-initialization. in parallel port operation, each byte is programmed individually.
ad9913 rev. 0 | page 24 of 32 data read operation a typical read operation follows the steps shown in figure 33 . 1. the user supplies pclk, cs , r/ w , and the parallel address of the register using the address pins (adr0 through adr7) for the read operation. 2. cs , r/ w , and the address lines must meet the setup and hold times relative to the 1 st pclk rising edge. 3. the user releases the bus to read. 4. the ad9913 drives data onto the bus after the second pclk rising edge. 5. cs must meet the set up and hold times to the 3 rd pclk rising edge. data write operation write operations work in a similar fashion as read operations except that the user drives the bus for both pclk cycles. a typical write access follows the steps shown in figure 34 . 1. the user supplies the pclk, cs , r/ w , and the parallel address of the register and using the address pins (adr0/d0 through adr7/d7). 2. cs , r/ w , and the address lines must meet the set up and hold times relative to the 1 st pclk rising edge. 3. data lines must meet the set up and hold times relative to the 2 nd pclk rising edge. 4. cs must meet the set up and hold times relative to the 3 rd pck rising edge. pclk read operation addr0 data0 data1 addr1 cs r/w addr/data 0.3ns t chd t csu t dvld t ahd t asu 3ns 0.3ns 8ns 3ns 07002-028 figure 33. parallel port read timing pclk write operation addr/data cs r/w data1 addr1 data0 addr0 0.3ns t chd 0.3ns t dhd 3ns t dsu 3ns t asu 0.3ns t ahd 3ns t csu 07002-029 figure 34. parallel port write timing
ad9913 rev. 0 | page 25 of 32 register map and bit descriptions register map note that the highest number found in the serial bit range column for each register in the following tables is the msb and the lowest number is the lsb for that register. table 9. control registers register name (serial address) [serial bit range]/ parallel address msb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb bit 0 default value [7:0]/0x00 external power- down mode digital power- down dac power- down clock input power- down load srr @ io_update autoclear auxiliary accum. autoclear phase accum. enable sine output 0x00 [15:8]/0x01 clear auxiliary accum. clear phase accum. destination [1:0] 00: frequency word 01: phase word auxiliary accumulator enable dc output active linear sweep state trigger active linear sweep no-dwell active 0x00 [23:16]/0x02 lsb first internal pr ofile control [2:0] sync clock disable open open direct switch mode active 0x00 cfr1 control function register 1 (0x00) [31:24]/0x03 open open open modulus enable use internal profile match pipe delays active open open 0x00 [7:0]/0x04 cmos clock mode crystal clock mode pll power- down pll lo range pll input div by 2 vco2 sel pll reset pll lock 0x32 cfr2 control function register 2 (0x01) [15:8]/0x05 pll output div by 2 pll multiplication factor [5:0] open 0x14 [7:0]/0x06 fs c [7:0] 0xff [15:8]/0x07 open open reserved open fsc [9:8] 0x13 [23:16]/0x08 reserved 0x7f dac control register (0x02) [31:24]/0x09 reserved 0x00 [7:0]/0x0a frequency tuning word [7:0] 0x00 [15:8]/0x0b frequency tuning word [15:8] 0x00 [23:16]/0x0c frequency tuning word [23:16] 0x00 ftw (0x03) [31:24]/0x0d frequency tuning word [31:24] 0x00 [7:0]/0x0e phase offset word [7:0] 0x00 pow (0x04) [15:8]/0x0f open [1:0] phase offset word [13:8] 0x00 [7:0]/0x12 sweep parameter word 0 [7:0] 0x00 [15:8]/0x13 sweep parame ter word 0 [15:8] 0x00 [23:16]/0x14 sweep parameter word 0 [23:16] 0x00 [31:24]/0x15 sweep parameter word 0 [31:24] 0x00 [39:32]/0x16 sweep parameter word 1 [7:0] 0x00 [47:40]/0x17 sweep parame ter word 1 [15:8] 0x00 [55:48]/0x18 sweep parameter word 1 [23:16] 0x00 linear sweep parameter register (0x06) [63:56]/0x19 sweep parameter word 1 [31:24] 0x00 [7:0]/0x1a rising delta word [7:0] 0x00 [15:8]/0x1b rising delta word [15:8] 0x00 [23:16]/0x1c rising delta word [23:16] 0x00 [31:24]/0x1d rising delta word [31:24] 0x00 [39:32]/0x1e falling delta word [7:0] 0x00 [47:40]/0x1f falling delta word [15:8] 0x00 [55:48]/0x20 falling delta word [23:16] 0x00 linear sweep delta parameter register (0x07) [63:56]/0x21 falling delta word [31:24] 0x00
ad9913 rev. 0 | page 26 of 32 register name (serial address) [serial bit range]/ parallel address msb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb bit 0 default value [7:0]/0x22 rising sweep ramp rate word [7:0] 0x00 [15:8]/0x23 rising sweep ramp rate word [15:8] 0x00 [23:16]/0x24 falling sweep ramp rate word [7:0] 0x00 linear sweep ramp rate register (0x08) [31:24]/0x25 falling sweep ramp rate word [15:8] 0x00 [7:0]/0x26 frequency tuning word [7:0] 0x00 [15:8]/0x27 frequency tuning word [15:8] 0x00 [23:16]/0x28 frequency tuning word [23:16] 0x00 [31:24]/0x29 frequency tuning word [31:24] 0x00 [39:32]/0x2a phase offset word [7:0] 0x00 profile 0 (0x09) [47:40]/0x2b open [1:0] phase offset word [13:8] 0x00 [7:0]/0x2c frequency tuning word [7:0] 0x00 [15:8]/0x2d frequency tuning word [15:8] 0x00 [23:16]/0x2e frequency tuning word [23:16] 0x00 [31:24]/0x2f frequency tuning word [31:24] 0x00 [39:32]/0x30 phase offset word [7:0] 0x00 profile 1 (0x0a) [47:40]/0x31 open [1:0] phase offset word [13:8] 0x00 [7:0]/0x32 frequency tuning word [7:0] 0x00 [15:8]/0x33 frequency tuning word [15:8] 0x00 [23:16]/0x34 frequency tuning word [23:16] 0x00 [31:24]/0x35 frequency tuning word [31:24] 0x00 [39:32]/0x36 phase offset word [7:0] 0x00 profile 2 (0x0b) [47:40]/0x37 open [1:0] phase offset word [13:8] 0x00 [7:0]/0x38 frequency tuning word [7:0] 0x00 [15:8]/0x39 frequency tuning word [15:8] 0x00 [23:16]/0x3a frequency tuning word [23:16] 0x00 [31:24]/0x3b frequency tuning word [31:24] 0x00 [39:32]/0x3c phase offset word [7:0] 0x00 profile 3 (0x0c) [47:40]/0x3d open [1:0] phase offset word [13:8] 0x00 [7:0]/0x3e frequency tuning word [7:0] 0x00 [15:8]/0x3f frequency tuning word [15:8] 0x00 [23:16]/0x40 frequency tuning word [23:16] 0x00 [31:24]/0x41 frequency tuning word [31:24] 0x00 [39:32]/0x42 phase offset word [7:0] 0x00 profile 4 (0x0d) [47:40]/0x43 open [1:0] phase offset word [13:8] 0x00 [7:0]/0x44 frequency tuning word [7:0] 0x00 [15:8]/0x45 frequency tuning word [15:8] 0x00 [23:16]/0x46 frequency tuning word [23:16] 0x00 [31:24]/0x47 frequency tuning word [31:24] 0x00 [39:32]/0x48 phase offset word [7:0] 0x00 profile 5 (0x0e) [47:40]/0x49 open [1:0] phase offset word [13:8] 0x00 [7:0]/0x4a frequency tuning word [7:0] 0x00 [15:8]/0x4b frequency tuning word [15:8] 0x00 [23:16]/0x4c frequency tuning word [23:16] 0x00 [31:24]/0x4d frequency tuning word [31:24] 0x00 [39:32]/0x4e phase offset word [7:0] 0x00 profile 6 (0x0f) [47:40]/0x4f open open phase offset word [13:8] 0x00 [7:0]/0x50 frequency tuning word [7:0] 0x00 [15:8]/0x51 frequency tuning word [15:8] 0x00 [23:16]/0x52 frequency tuning word [23:16] 0x00 [31:24]/0x53 frequency tuning word [31:24] 0x00 [39:32]/0x54 phase offset word [7:0] 0x00 profile 7 (0x10) [47:40]/0x55 open open phas e offset word [13:8] 0x00
ad9913 rev. 0 | page 27 of 32 register bit descriptions the serial i/o port registers span an address range of 0 to 16 (0x00 to 0x10 in hexadecimal notation). this represents a total of 17 registers. however, one of these registers (0x05) is unused, yielding a total of 16 available registers. the registers are not of uniform depth; each contains the number of bytes necessary for its particular function. additionally, the registers are assigned names according to their functionality. in some cases, a register is given a mnemonic descriptor. for example, the register at serial address 0x00 is named control function register 1 and is assigned the mnemonic cfr1. the following section provides a detailed description of each bit in the ad9913 register map. for cases in which a group of bits serve a specific function, the entire group is considered as a binary word and described in aggregate. this section is organized in sequential order of the serial addresses of the registers. each subheading includes the register name and optional register mnemonic (in parentheses). also given is the serial address in hexadecimal format and the number of bytes assigned to the register. following each subheading is a table containing the individual bit descriptions for that particular register. the location of the bit(s) in the register are indicated by a single number or a pair of numbers separated by a colon. a pair of numbers (a:b) indicates a range of bits from the most significant (a) to the least significant (b). for example, 5:2 implies bit position 5 down to bit position 2, inclusive, with bit 0 identifying the lsb of the register. unless otherwise stated, programmed bits are not transferred to their internal destinations until the assertion of the i/o_update pin or a profile change. control function register 1 (cfr1) address 0x00; 4 bytes are assigned to this register. table 10. bit description for cfr1 bit(s) bit name description 31:29 open leave these bits at their default values. this bit is ignored if linear sweep is disabled. 0 = the auxiliary accumulator is used for linear sweep generation. 28 modulus enable 1 = the auxiliary accumulator is used for programmable modulus. 27 use internal profile 0 = profiles are controlled by profile pins; only valid in serial mode. 1 = profiles are controlled by cfr1 [22:20]. 26 match pipeline delays active 0 = the latency across the auxiliary accumulator, the phase offset word, and phase accumulator are matched. 1 = the latency across the auxiliary accumulator, the phase offset word, and phase accumulator are not matched. 25:24 open leave these bits at the default values. 0 = msb first format is used. 23 lsb first 1 = lsb first format is used. 22:20 internal profile control ineffective unless bit 27 = 1. default is 000 2 . refer to the linear sweep mode section for details on how to program these registers during linear sweep, and refer to the direct switch mode section for details on how to program these registers in direct switch mode. 19 sync clock disable 0 = the sync_clk pin is active. 1 = the sync_clk pin assumes a static logic 0 st ate (disabled). in this state, the pin drive logic is shut down, minimizing the noise generated by the digital circuitry. 18:17 open leave these bits in their default values. 16 direct switch mode active 0 = direct switch mode is disabled. 1 = direct switch mode is enabled. 0 = normal operation of the auxiliary accumulator (default). 15 clear auxiliary accumulator 1 = asynchronous, static reset of the auxiliar y accumulator. the ramp accumulator remains reset as long as this bit remains set. this bit is synchronized with either an i/o update or a profile change and the next rising edge of sync_clk. 0 = normal operation of the dds phase accumulator (default). 14 clear phase accumulator 1 = asynchronous, static reset of the dds phase accumulator.
ad9913 rev. 0 | page 28 of 32 bit(s) bit name description 00 = in direct switch mode, use this setting for fsk. in linear sweep mode, the auxiliary accumulator is used for frequency sweeping. in programmable modulus mode, these bits must be 00. 13:12 destination 01 = in direct switch mode, use this setting for psk. in linear sweep mode, the auxiliary accumulator is used for phase sweeping. 11 auxiliary accumulator enable 0 = auxiliary accumulator is inactive. 1 = auxiliary accumulator is active. 10 dc output active this bit is ignored if linear sweep is disabled (see cfr1 [11]). 0 = normal operating state. 1 = the output of the dac is driven to full-scale and the dds output is disabled. 9 linear sweep state trigger active 0 = edge triggered mode active. 1 = state triggered mode active. 8 linear sweep no-dwell active this bit is ignore d if linear sweep is disabled (see cfr1[11]). 0 = when a sweep is completed, the device holds at the final state. 1 = when a sweep is completed, the device reverts to the initial state. 7 external power-down mode 0 = the external power-down mode selected is the fast recovery power-down mode. in this mode, when the pwr_dwn_ctl input pin is hi gh, the digital logic and the dac digital logic are powered down. the dac bias circuitry, comparator, pll, oscillator, and clock input circuitry are not powered down. 1 = the external power-down mode selected is the full power-down mode. in this mode, when the pwr_dwn_ctl pin is high, all functions are powered down. this includes the dac and pll, which take a significant amount of time to power up. 6 digital power-down 0 = the digital core is enabled for operation. 1 = the digital core is disabled and is in a low power dissipation state. 5 dac power-down 0 = the dac is enabled for operation. 1 = the dac is disabled and is in its lowest power dissipation state. 4 clock input power-down 0 = normal operation. 1 = shut down all clock generation including the system clock signal going into the digital section. 3 load srr @ io_update 0 = every time the linear sweep rate register is updated, the ramp rate timer keeps its operation until it times out and then loads the update value into the timer. 1 = the timer is interrupted immediately upon the assertion of io_update and the value is loaded. 2 autoclear auxiliary accumulator 0 = normal operation. 1 = the auxiliary accumulator is synchronously cleared (zero is loaded) for one cycle upon receipt of the io_update sequence indicator. 1 autoclear phase accumulator 0 = normal operation. 1 = the phase accumulator is synchronously cleared for one cycle upon receipt of the io_update sequence indicator. 0 enable sine output 0 = the angle-to-amplitude conversion logic employs a cosine function. 1 = the angle-to-amplitude conversion logic employs a sine function.
ad9913 rev. 0 | page 29 of 32 control function register 2 (cfr2) address 0x01; 2 bytes are assigned to this register. table 11. bit descriptions for cfr2 bit(s) bit name description 15 pll output div by 2 14:9 pll multiplication factor see table 7 for details on multiplication factor configuration. 8 open leave this bit at the default state. 7 cmos clock mode see table 6 for directions on programming this bit. 6 crystal clock mode see table 6 for directions on programming this bit. 5 pll power-down 0 = pll is active 1 = pll is inactive and in its lowest power state 4 pll lo range 0 = use this setting for pll if the pll reference frequency is >5 mhz. 1 = use this setting for pll if the pll reference frequency is <5 mhz. 3 pll input div by 2 0 = the pll reference frequency = the ref_clk input frequency. 1 = the pll reference frequency = ? the ref_clk input frequency. 2 0 = use this setting for vco frequencies below 100 mhz and/or to optimize for power rather than performance. vco2 sel 1 = use this setting to optimize for performance; this setting results in slightly higher power consumption. note: when setting this bi t, an io_update must occur within 40 s of the pll power-down bit (cfr2 [5]) going low. 1 pll reset 0 = the pll logic is reset and no n-operational until this bit is set. 1 = the pll logic operates normally. 0 pll lock this read-only bit is se t when the ref_clk pll is locked. dac control register address 0x02; 4 bytes are assigned to this register. table 12. bit descriptions for dac control register bit(s) bit name description 15:14, 10 open leave these bits at their default state. 9:0 fsc this 10-bit number controls the full-scale output current of the dac. 31:16,13:11 reserved leave these bits at their default state. frequency tuning word register (ftw) address 0x03, 4 bytes are assigned to this register. table 13. bit descriptions for ftw register bit(s) bit name description 31:0 frequency tuning word 32-bit frequency tuning word. phase offset word register (pow) address 0x04, 2 bytes are assigned to this register. table 14. bit descriptions for pow register bit(s) bit name description 15:14 open leave these bits at their default state. 13:0 phase offset word 14-bit phase offset word.
ad9913 rev. 0 | page 30 of 32 linear sweep parameter register address 0x06, 8 bytes are assigned to this register. this register is only effective if cfr1 [11] or cfr1 [28] are set. see the auxiliary accumulator section. table 15. bit descriptions for linear sweep limit register bit(s) bit name description 63:32 sweep parameter word 0 32-bit linear sweep upper limit value. in modulus mode, these bits set the auxiliary accumulator capacity 31:0 sweep parameter word 1 32-bit linear sweep lower limit value. in modulus mode, these bits set the base ftw. linear sweep delta parameter register address 0x07, 8 bytes are assigned to this register. this register is only effective if cfr1 [11] or cfr1 [28] are set. see the auxiliary accumulator section. table 16. bit descriptions for linear sweep step size register bit(s) bit name description 63:32 falling delta word 32-bit linear sweep decrement step size value. 31:0 rising delta word 32-bit linear sweep increment step size value. in modulus mode, these bits set the auxiliary accumulator seed value. linear sweep ramp rate register address 0x08, 4 bytes are assigned to this register. this register is only effective if cfr1 [11] or cfr1 [28] are set. see the auxiliary accumulator section. table 17. bit descriptions for linear sweep rate register bit(s) bit name description 31:16 falling sweep ramp rate 16-bit linear sweep negative slope value that defines the time interval between decrement values. 15:0 rising sweep ramp rate 16-bit linear sweep positive slope value that defines the time interval between increment values. profile registers there are eight consecutive serial i/o addresses dedicated to device profiles. in normal operation, the active profile register is selected using the external profile select pins. profile 0 to profile 7single tone register address 0x09 to address 0x10, 6 bytes are assigned to these registers. table 18. bit descriptions for profile 0 to profile 7 single tone register bit(s) bit name description 47:46 open leave these bits at their default state. 45:32 phase offset word this 14-bit number controls the dds phase offset. 31:0 frequency tuning word this 32-bit number controls the dds frequency.
ad9913 outline dimensions compliant to jedec standards mo-220-vhhd-2 0.30 0.23 0.18 0.20 ref 0.80 max 0.65 typ 0.05 max 0.02 nom 12 max 1.00 0.85 0.80 seating plane coplanarity 0.08 1 32 8 9 25 24 16 17 0.50 0.40 0.30 3.50 ref 0.50 bsc pin 1 indicator top view 5.00 bsc sq 4.75 bsc sq 3.25 3.10 sq 2.95 pin 1 indicator 0.60 max 0.60 max 0.25 min exposed pad (bottom view) figure 35. 32-lead frame chip scale package [lfcsp_vq] 5 mm 5 mm body, very thin quad (cp-32-2) dimensions shown in millimeters ordering guide model temperature range package description package option ad9913bcpz C40c to +85c 32-lead frame chip scale package [lfcsp_vq] cp-32-2 1 ad9913bcpz-reel7 C40c to +85c 32-lead frame chip scale package [lfcsp_vq] cp-32-2 1 ad9913/pcbz evaluation board 1 1 z = rohs compliant part.
ad9913 rev. 0 | page 32 of 32 notes ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d07002-0-10/07(0)

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